1. Field of Invention
This invention pertains to the field of computer systems and more specifically to an apparatus for introducing wait states into a memory access.
2. History of the Prior Art
Computer systems including a microprocessor, a dynamic random access memory (DRAM), a memory control unit (MCU) and support for in-circuit-emulation (ICE) are well known in the prior art. A typical ICE-system in operation includes an ICE-base, a cable coupling the ICE-base to the target microprocessor in the computer system, and a host computer that provides the user interface. The cable comprises a number of channels and is used to transfer the trace-data from the target microprocessor and to send commands to the target microprocessor from the ICE-system. The host computer is connected to the ICE-base and provides the user-interface to view data and to be able to send commands.
The MCU is usually coupled to the microprocessor by a bus. The MCU interfaces with the microprocessor and interacts with the DRAM to service the read and write requests from the microprocessor. The DRAM typically includes several banks of memory. Each of the memory banks may support different speeds of operation. In such instances, a memory bank control register (MBCR) disposed in the MCU is used and is set to values that correspond to the speed of operation of the associated memory bank. The MCU also normally includes circuitry for accepting the values in the MBCRs to generate control signals to the memory banks to service read and write requests.
In some prior art computer systems multiplexed addressed buses have been used. Intel's 486SLC is an example of one such processor. In these systems, each half of the memory address is transferred in two successive clock cycles. Thus the memory accesses typically take at least two clock cycles. However, the processor supports a Fast Column Address Strobe (fast-CAS) mode of operation in which the access time is reduced to one clock cycle in the steady state. This is accomplished by using a special signal in the MCU which indicates if the row address of the present operation is the same as that of the previous access. In this case, only the column address is transmitted. Thus, the memory accesses are accomplished in one clock cycle in the steady-state.
When the computer system is operating in conjunction with the ICE-system, it may be operating either in ICE-mode or ICE-user-mode. In the ICE-mode, the processor in the computer system executes code sent by the ICE-system. In the ICE-user-mode, the user code resident in the computer memory is executed. In the ICE-user-mode, the address and data buses are traced and the data is transferred to the ICE-base.
When the memory bank is operating in the fast-CAS mode and the processor is operating in the ICE-user-mode, the ICE-system usually does not have sufficient time to transfer the trace data from the target processor to the ICE-base. This is because trace of data and address are interleaved on the same bus and a memory access trace operation takes two packets that need to be transferred in two clock cycles. Changing the values in the MBCR to slow down the memory access cannot be relied upon since the basic input/output system (BIOS) or other system software may overwrite the values changed. Increasing the number of channels in the ICE system may be cost-prohibitive or may require major engineering changes.
What is needed then is a way to increase the memory access time transparent to the values in the MBCR when the target processor is in the ICE-user-mode. Such a system should be able to provide the ICE-system with sufficient time to transfer data from the target computer system to the ICE-base without causing any degradation in performance when the target processor is not operating in the ICE-user-mode.